Generally, semiconductor lithography includes integrated circuits built on a substrate, in a layer by layer fashion. The structure of a layer is formed by transferring a lithographically printed pattern from a light sensitive resist film onto a film of circuit material. A resist film on the substrate is imprinted by exposing it with a densely patterned lithographic image of the circuit structure. A lithographic image is an optically demagnified image of a stencil mask. The light pattern which illuminates the mask (“the source”) is carefully designed along with the mask shapes to improve resolution. The source pattern is directional. The illuminating intensity is specified, for example, in each of about 200 different directions, wherein the illumination is spatially uniform across the mask. Each direction may be mirrored symmetrically into directional quadrants, for example, with the beam from each direction being mirrored across one meridional plane that contains the mask normal and the horizontal axis of the mask plane, and across a second meridional plane that contains the mask normal and the vertical axis of the mask plane.
In the semiconductor manufacturing industry, semiconductor manufacturers typically try to provide steady improvements in circuit density. Unfortunately, the exposure tools that are used to form circuit patterns have approached technological limits, and have increased in costs. Thus, one drawback in current semiconductor manufacturing is that the exposure tools provide little or no direct opportunity to provide incremental increases in circuit density. As a result, efforts to increase circuit density are focused on optimizing existing lithographic processes to make maximum use of available imaging resolution.
Existing mask data preparation logistics provide a partial framework for applying optimization to the design of mask shapes. One such process involves distributing the design of different mask regions across large numbers of processors (for example, 10K cores in the next generation of high-end dataprep hardware), considering at a fundamental level the different regions to be effectively isolated in terms of short-range interaction between different mask features. However, it is known that superior images can be achieved in optimized lithography by also including within the optimization process the directional distribution of the light that illuminates the mask, along with the variables that define the mask. Typically, the illumination pattern consists of ˜100 UV light beams having independently adjustable intensity, each of which illuminates the entire mask from a particular direction. One problem with this approach is the illumination variables thus couple all mask variables together across the entire mask, making it impossible to distribute the combined mask plus illumination optimization problem across multiple processors in a simple manner. Other long-range factors pose the same difficulty (e.g., rule parameters for assisting-feature generation). This coupling from long-range factors poses a significant limitation for known methods of semiconductor manufacturing, for instance, the illumination pattern (“source”) is only optimized across a very limited sample of critical layout patterns whose area is kept small enough to be processed using a single Central Processing Unit (CPU). One approach directed to this problem is to sequentially iterate between optimization of the mask (fixed source), and optimization of the source (fixed mask). However, such a limited approach can yield poor solutions compared with jointly co-optimizing the mask and source variables together. Unfortunately, current technology only allows a very small fraction of the total mask area to be co-optimized with the source.
One known source mask optimization (SMO) scheme co-optimizes the source against a limited number of mask patterns (“clips”). As used herein, a “mask clip” refers to features on at least one of the masks used to form an integrated circuit, or to form a region of an integrated circuit. As used herein, a “clip” or a “circuit clip” refers to a separate set of features in a semiconductor circuit. In this instance, the source is jointly optimized with multiple sample mask regions, each such clip being several times larger than the lens resolution. Mask variables in all clips are coupled together by source variables, hence the source must be optimized together with all mask clips. Further, the above need for combined processing makes parallelization challenging. Each source variable represents a directional component which illuminates the entire mask.
In one design example for semiconductor manufacturing, full SMO includes a number of patterns that are considered when the source is designed, but the practical limit in a joint optimization (JO) step may be a few hundred clips, and is difficult to parallelize. Large distributed memory machines (˜1000 nodes) are currently used to design masks using non-NLP iterative edge re-positionings, sometimes referred to as Optical Proximity Correction (OPC); however, the source has to be fixed. SMO methodology typically assumes that the core JO optimization can be warm-started.
Known initial mask and source patterns can be inputted in one of several representations, whose entries represent problem factors (i.e., variables) with initial values. The variables may include, for example: pixel intensities in pupil grid (source); pixel amplitudes in a bitmap (mask); amplitudes in collectable mask diffraction orders (mask); polygons with edges at specified positions (mask); rules for positioning the edges of certain kinds of frequently deployed non-printing assist features (mask). Additionally, pattern variables (factors) that are long-range, and those that are short-range (spatially local) may be distinguished. Models may be available that describe the relationship between the mask and source variables, and the features that are printed in an integrated circuit being fabricated. Standard lithographic objectives can be evaluated using these models, for example expressing the deviation of the printed feature from a target, or the severity of such deviations in the presence of process fluctuations. Circuit and patterning requirements can also be expressed using these models, for example, expressing that the deviation of the printed feature from a target can be no larger than a specified requirement.
There is therefore a need to increase circuit density on a substrate for manufacturing semiconductors, for example, by optimizing use of existing technology. It would further be desirable to provide optimization methods in the field of lithography to increase circuit density in semiconductor manufacturing.